HRF3205, HRF3205S Data Sheet June 1999 File Number 4447.4 100A, 55V, 0.008 Ohm, N-Channel, Power MOSFETs These are N-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. NOTE: Calculated continuous current based on maximum allowable junction temperature. Package limited to 75A continuous, see Figure 9. Features ? 100A, 55V (See Note) ? Low On-Resistance, rDS(ON) = 0.008 ? Temperature Compensating PSPICE? Model ? Thermal Impedance SPICE Model ? UIS Rating Curve ? Related Literature - TB334, "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol D Ordering Information PART NUMBER HRF3205 HRF3205S PACKAGE TO-220AB TO-263AB BRAND HRF3205 HRF3205S G S NOTE: When ordering, use the entire part number. Add the suffix T to obtain the TO-263AB variant in tape and reel, e.g., HRF3205ST. Packaging JEDEC TO-220AB SOURCE DRAIN GATE DRAIN (FLANGE) GATE SOURCE JEDEC TO-263AB DRAIN (FLANGE) 4-29 CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE? is a registered trademark of MicroSim Corporation. http://www.intersil.com or 407-727-9207 | Copyright ? Intersil Corporation 1999 HRF3205, HRF3205S Absolute Maximum Ratings TC = 25oC, Unless Othewise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VGS Drain Current Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 55 55 ?20V 100 390 Figure 10 175 1.17 -55 to 175 300 260 V V V A A W W/oC oC oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 150oC. Electrical Specifications PARAMETER TC = 25oC, Unless Otherwise Specified SYMBOL BVDSS VGS(TH) IDSS TEST CONDITIONS ID = 250?A, VGS = 0V VGS = VDS, ID = 250?A VDS = 55V, VGS = 0V VDS = 44V, VGS = 0V, TC = 150oC VGS = ?20V Reference to 25oC, ID = 250?A ID = 59A, VGS = 10V (Figure 4) VDD = 28V, ID 59A, RL = 0.47, VGS = 10V, RGS = 2.5 MIN 55 2 VDD = 44V, ID 59A, VGS = 10V, Ig(REF) = 3mA (Figure 6) VDS = 25V, VGS = 0V, f = 1MHz (Figure 5) Measured From the Contact Modified MOSFET Screw on Tab to Center of Die Symbol Showing the Internal Devices InMeasured From the Drain ductances Lead, 6mm (0.25in) From D Package to Center of Die Measured From the Source Lead, 6mm (0.25in) From Header to Source Bonding Pad LD G LS S TYP 0.057 0.0065 14 100 43 70 4000 1300 480 7.5 MAX 4 25 250 100 0.008 170 32 74 - UNITS V V ?A ?A nA V ns ns ns ns nC nC nC pF pF pF nH Drain to Source Breakdown Voltage Gate to Source Threshold Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current Breakdown Voltage Temperature Coefficient Drain to Source On Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate to Source Charge Gate to Drain "Miller" Charge Input Capacitance Output Capacitance Reverse Transfer Capacitance Internal Source Inductance IGSS V(BR)DSS/ TJ rDS(ON) td(ON) tr td(OFF) tf Qg Qgs Qgd CISS COSS CRSS LS - Internal Drain Inductance LD - 4.5 - nH Thermal Resistance Junction to Case Thermal Resistance Junction to Ambient RJC RJA TO-220 TO-263 (PCB Mount, Steady State) - - 0.85 62 40 oC/W oC/W oC/W 4-30 HRF3205, HRF3205S Source to Drain Diode Specifications PARAMETER Continuous Source to Drain Current Pulsed Source to Drain Current (Note 2) SYMBOL ISD ISDM TEST CONDITIONS MOSFET Symbol Showing The Integral Reverse P-N Junction Diode D MIN - TYP - MAX 100 (Note 1 390 UNITS A A G S Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge NOTE: VSD trr QRR ISD = 59A (Note 4) ISD = 59A, dISD/dt = 100A/?s (Note 4) ISD = 59A, dISD/dt = 100A/?s (Note 4) - 110 450 1.3 170 680 V ns nC 2. Repetitive rating; pulse width limited by maximum junction temperature (See Figure 11) Typical Performance Curves 1000 ID, DRAIN TO SOURCE CURRENT (A) VGS IN DECENDING ORDER 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 100 4.5V 1000 ID, DRAIN TO SOURCE CURRENT (A) VGS IN DECENDING ORDER 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 100 4.5V 10 0.1 20?s PULSE WIDTH TC = 25oC 1.0 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 10 0.1 20?s PULSE WIDTH TC = 175oC 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 1. OUTPUT CHARACTERISTICS FIGURE 2. OUTPUT CHARACTERISTICS 1000 ID, DRAIN TO SOURCE CURRENT(A) NORMALIZED DRAIN TO SOURCE ON RESISTANCE 2.5 ID = 98A, VGS = 10V PULSE DURATION = 80?s DUTY CYCLE = 0.5% MAX 2.0 100 TJ = 25oC 1.5 10 TJ = 175oC 1.0 1 3 4.5 6 VDS = 25V PULSE DURATION = 80?s DUTY CYCLE = 0.5% MAX 7.5 9 0.5 0 -80 -40 VGS, GATE TO SOURCE VOLTAGE (V) 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) 200 FIGURE 3. TRANSFER CHARACTERISTICS FIGURE 4. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 4-31 HRF3205, HRF3205S Typical Performance Curves 8000 VGS, GATE TO SOURCE VOLTAGE (V) 7000 C, CAPACITANCE (pF) 6000 5000 CISS 4000 3000 COSS 2000 1000 0 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 CRSS VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGS (Continued) 20 ID = 59A VDS = 28V 16 VDS = 11V 12 VDS = 44V 8 4 0 0 36 72 108 144 180 Qg , GATE CHARGE (nC) FIGURE 5. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 6. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT 1000 ISD, REVERSE DRAIN CURRENT(A) PULSE DURATION = 80?s DUTY CYCLE = 0.5% MAX TJ = 175oC 1000 100 ID, DRAIN CURRENT (A) 10?s 100 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 100?s 1ms 10ms 10 TJ = 25oC 10 1 0.5 1.0 1.5 2.0 VSD, SOURCE TO DRAIN VOLTAGE (V) 1 1 VDSS(MAX) = 55V 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 FIGURE 7. SOURCE TO DRAIN DIODE FORWARD VOLTAGE FIGURE 8. FORWARD BIAS SAFE OPERATING AREA 120 1000 IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 90 If R = 0 tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD) If R 0 tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1] 60 100 STARTING TJ = 25oC 30 CURRENT LIMITED BY PACKAGE 0 25 50 75 100 125 150 175 STARTING TJ = 150oC TC, CASE TEMPERATURE (oC) 10 0.01 0.1 1 10 tAV, TIME IN AVALANCHE (ms) 100 FIGURE 9. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE FIGURE 10. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY 4-32 HRF3205, HRF3205S Typical Performance Curves 10 DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 (Continued) THERMAL IMPEDANCE ZJC, NORMALIZED 1 PDM 0.1 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 10-3 10-2 10-1 t, RECTANGULAR PULSE DURATION (s) 100 101 0.01 SINGLE PULSE 10-5 10-4 FIGURE 11. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE Test Circuits and Waveforms VDS BVDSS L VARY tP TO OBTAIN REQUIRED PEAK IAS VGS DUT tP RG IAS VDD tP VDS VDD + 0V IAS 0.01 0 tAV FIGURE 12. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 13. UNCLAMPED ENERGY WAVEFORMS VDS RL VDD Qg(TOT) Qgd Qgs VGS VGS + VDD DUT IG(REF) IG(REF) 0 0 VDS FIGURE 14. GATE CHARGE TEST CIRCUIT FIGURE 15. GATE CHARGE WAVEFORM 4-33 HRF3205, HRF3205S Test Circuits and Waveforms VDS (Continued) tON td(ON) RL VDS + tOFF td(OFF) tr tf 90% 90% VGS DUT RGS VDD 0 10% 90% 10% VGS VGS 0 10% 50% PULSE WIDTH 50% FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS 4-34 HRF3205, HRF3205S PSPICE Electrical Model SUBCKT HRF3205P3 2 1 3 ; CA 12 8 4.9e-9 CB 15 14 4.9e-9 CIN 6 8 3.45e-9 10 rev 7/25/97 LDRAIN DPLCAP 5 RLDRAIN DBREAK 11 + 17 EBREAK 18 MWEAK MMED MSTRO CIN LSOURCE 8 RSOURCE RLSOURCE S1A 12 S1B CA 13 + EGS 6 8 EDS 13 8 S2A 14 13 S2B CB + 5 8 8 22 RVTHRES 14 IT VBAT + 15 17 RBREAK 18 RVTEMP 19 7 SOURCE 3 DRAIN 2 RSLC1 51 ESLC 50 RDRAIN EVTHRES + 19 8 6 21 16 RSLC2 5 51 EBREAK 11 7 17 18 57 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1 IT 8 17 1 GATE 1 ESG + LGATE EVTEMP RGATE + 18 22 9 20 6 8 LDRAIN 2 5 1e-9 LGATE 1 9 2.6e-9 LSOURCE 3 7 1.1e-9 K1 LGATE LSOURCE 0.0085 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD RLGATE RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 3.5e-4 RGATE 9 20 0.36 RLDRAIN 2 5 10 RLGATE 1 9 26 RLSOURCE 3 7 11 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 4.5e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*550),3))} .MODEL DBODYMOD D (IS = 4.25e-12 RS = 1.8e-3 TRS1 = 2.75e-3 TRS2 = 5e-6 CJO = 5.95e-9 TT = 4e-7 M = 0.55) .MODEL DBREAKMOD D (RS = 0.06 IKF = 30 TRS1 = -3e-3 TRS2 = 3e-6) .MODEL DPLCAPMOD D (CJO = 4.45e-9 IS = 1e-30 N = 1 M = 0.88 VJ = 1.45) .MODEL MMEDMOD NMOS (VTO = 2.93 KP = 9.5 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1) .MODEL MSTROMOD NMOS (VTO = 3.23 KP = 150 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 2.35 KP = 0.02 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 10) .MODEL RBREAKMOD RES (TC1 = 8e-4 TC2 = 4e-6) .MODEL RDRAINMOD RES (TC1 = 8e-2 TC2 = 5e-6) .MODEL RSLCMOD RES (TC1 = 1e-4 TC2 = 1.05e-6) .MODEL RSOURCEMOD RES (TC1 = 1e-4 TC2 = 1.5e-5) .MODEL RVTHRESMOD RES (TC1 = -2.3e-3 TC2 = -1.2e-5) .MODEL RVTEMPMOD RES (TC1 = -2.2e-3 TC2 = -7e-6) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -9 VOFF= -4) VON = -4 VOFF= -9) VON = 0 VOFF= 2.5) VON = 2.5 VOFF= 0) NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 4-35 + - DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DPLCAP 10 5 DPLCAPMOD DBODY HRF3205, HRF3205S SPICE Thermal Model REV 25 July 97 HRF3205 CTHERM1 7 6 2.53e-5 CTHERM2 6 5 1.38e-3 CTHERM3 5 4 7.00e-3 CTHERM4 4 3 2.50e-2 CTHERM5 3 2 1.33e-1 CTHERM6 2 1 5.75e-1 RTHERM1 7 6 7.78e-4 RTHERM2 6 5 8.55e-3 RTHERM3 5 4 3.00e-2 RTHERM4 4 3 1.42e-1 RTHERM5 3 2 2.65e-1 RTHERM6 2 1 2.33e-1 RTHERM1 CTHERM1 7 JUNCTION 6 RTHERM2 CTHERM2 5 RTHERM3 CTHERM3 4 RTHERM4 CTHERM4 3 RTHERM5 CTHERM5 2 RTHERM6 CTHERM6 1 CASE All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. 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