54ACT 74ACT823 9-Bit D Flip-Flop March 1993 54ACT 74ACT823 9-Bit D Flip-Flop General Description The 'ACT823 is a 9-bit buffered register It features Clock Enable and Clear which are ideal for parity bus interfacing in high performance microprogramming systems The 'ACT823 offers noninverting outputs and is fully compatible with AMD's Am29823 Features Y Y Y Y Outputs source sink 24 mA TRI-STATE outputs for bus interfacing Inputs and outputs are on opposite sides 'ACT823 has TTL-compatible inputs Logic Symbols IEEE IEC Connection Diagrams Pin Assignment for DIP Flatpak and SOIC TL F 9894?1 TL F 9894 ? 2 TL F 9894 ? 3 Pin Assignment for LCC Pin Names D0 ? D8 O0 ? O8 OE CLR CP EN Description Data Inputs Data Outputs Output Enable Clear Clock Input Clock Enable TL F 9894 ? 4 FACTTM is a trademark of National Semiconductor Corporation TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9894 RRD-B30M75 Printed in U S A Functional Description The 'ACT823 consists of nine D-type edge-triggered flipflops These have TRI-STATE outputs for bus systems organized with inputs and outputs on opposite sides The buffered clock (CP) and buffered Output Enable (OE) are common to all flip-flops The flip-flops will store the state of their individual D inputs that meet the setup and hold time requirements on the LOW-to-HIGH CP transition With OE LOW the contents of the flip-flops are available at the outputs When OE is HIGH the outputs go to the high impedance state Operation of the OE input does not affect Function Table Inputs OE H H H L H L H H L L CLR X X L L H H H H H H EN L L X X H H L L L L CP L L X X X X L L L L D L H X X X X L H L H Internal Q L H L L NC NC L H L H Output O Z Z Z L Z NC Z Z L H High Z High Z Clear Clear Hold Hold Load Load Load Load Function the state of the flip-flops In addition to the Clock and Output Enable pins there are Clear (CLR) and Clock Enable (EN) pins These devices are ideal for parity bus interfacing in high performance systems When CLR is LOW and OE is LOW the outputs are LOW When CLR is HIGH data can be entered into the flip-flops When EN is LOW data on the inputs is transferred to the outputs on the LOW-to-HIGH clock transition When the EN is HIGH the outputs do not change state regardless of the data or clock input transitions H e HIGH Voltage Level L e LOW Voltage Level X e Immaterial Z e High Impedance L e LOW-to-HIGH Transition NC e No Change Logic Diagram TL F 9894 ? 5 Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays 2 Absolute Maximum Ratings (Note 1) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications b 0 5V to 7 0V Supply Voltage (VCC) DC Input Diode Current (IIK) b 20 mA VI e b0 5V a 20 mA VI e VCC a 0 5V b 0 5V to VCC a 0 5V DC Input Voltage (VI) DC Output Diode Current (IOK) b 20 mA VO e b0 5V a 20 mA VO e VCC a 0 5V b 0 5V to VCC a 0 5V DC Output Voltage (VO) g 50 mA DC Output Source or Sink Current (IO) DC VCC or Ground Current g 50 mA per Output Pin (ICC or IGND) b 65 C to a 150 C Storage Temperature (TSTG) Junction Temperature (TJ) CDIP 175 C PDIP 140 C Note 1 Absolute maximum ratings are those values beyond which damage to the device may occur The databook specifications should be met without exception to ensure that the system design is reliable over its power supply temperature and output input loading variables National does not recommend operation of FACT TM circuits outside databook specifications Recommended Operating Conditions Supply Voltage (VCC) 'ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) 74ACT 54ACT Minimum Input Edge Rate (DV Dt) 'ACT Devices VIN from 0 8V to 2 0V VCC 4 5V 5 5V 4 5V to 5 5V 0V to VCC 0V to VCC b 40 C to a 85 C b 55 C to a 125 C 125 mV ns DC Electrical Characteristics 74ACT Symbol Parameter VCC (V) 45 55 45 45 45 TA e 25 C Typ VIH VIL VOH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level 15 15 15 15 4 49 5 49 20 20 08 08 44 54 3 86 4 86 0 001 0 001 01 01 0 36 0 36 g0 1 g0 5 54ACT 74ACT Conditions TA e TA e b 55 C to a 125 C b 40 C to a 85 C Units Guaranteed Limits 20 20 08 08 44 54 3 70 4 70 01 01 0 50 0 50 g1 0 g 10 0 20 20 08 08 44 54 3 76 4 76 01 01 0 44 0 44 g1 0 g5 0 V V V VOUT e 0 1V or VCC b0 1V VOUT e 0 1V or VCC b0 1V IOUT e b50 mA VIN e VIL or VIH b 24 mA IOH b 24 mA IOUT e 50 mA VIN e VIL or VIH IOL 24 mA 24 mA VI e VCC GND VI e VIL VIH VO e VCC GND VI e VCC b2 1V VOLD e 1 65V Max VOHD e 3 85V Min VIN e VCC or GND 45 VOL Maximum Low Level Output Voltage 45 55 45 55 IIN IOZ ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum TRI-STATE Current Maximum ICC Input Minimum Dynamic Output Current Maximum Quiescent Supply Current 55 55 55 55 55 55 06 V V V mA mA mA mA mA mA 16 50 b 50 15 75 b 75 80 160 80 All outputs loaded thresholds on input associated with output under test Maximum test duration 2 0 ms one output loaded at a time Note ICC limit for 54ACT 25 C is identical to 74ACT 25 C 3 AC Electrical Characteristics 74ACT Symbol Parameter VCC (V) Min fmax tPLH tPHL tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CP to On Propagation Delay CP to On Propagation Delay CLR to On Output Enable Time OE to On Output Enable Time OE to On Output Disable Time OE to On Output Disable Time OE to On 50 50 50 50 50 50 50 50 120 15 20 25 15 20 15 15 TA e a 25 C CL e 50pF Typ 158 55 55 80 60 65 65 60 95 95 13 5 10 5 11 0 11 0 10 5 Max 54ACT TA e b55 C to a 125 C CL e 50 pF Min 95 15 15 15 15 15 15 15 12 0 12 0 18 0 11 5 12 0 13 5 12 0 Max 74ACT TA e b40 C to a 85 C CL e 50 pF Min 109 15 15 20 15 15 15 15 10 5 10 5 15 5 11 5 12 0 12 0 11 5 Max MHz ns ns ns ns ns ns ns Units Voltage Range 5 0 is 5 0V g 0 5V AC Operating Requirements 74ACT Symbol Parameter VCC (V) TA e a 25 C CL e 50 pF Typ ts th ts th tw tw trec Setup Time HIGH or LOW D to CP Hold Time HIGH or LOW Dn to CP Setup Time HIGH or LOW EN to CP Hold Time HIGH or LOW EN to CP CP Pulse Width HIGH or LOW CLR Pulse Width LOW CLR to CP Recovery Time 50 50 50 50 50 50 50 05 0 0 0 25 30 15 25 25 20 10 45 55 35 54ACT TA e b55 C to a 125 C CL e 50 pF 74ACT TA e b40 C to a 85 C CL e 50 pF Units Guaranteed Minimum 40 30 40 30 60 70 45 25 25 25 10 55 55 40 ns ns ns ns ns ns ns Voltage Range 5 0 is 5 0V g 0 5V Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 45 44 Units pF pF Conditions VCC e OPEN VCC e 5 0V 4 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows 74ACT Temperature Range Family 74ACT e Commercial TTL-Compatible 54ACT e Military TTL-Compatible Device Type Package Code SP e Slim Plastic DIP SD e Slim Ceramic DIP F e Flatpak L e Leadless Ceramic Chip Carrier (LCC) S e Small Outline (SOIC) 823 P C QR Special Variations X e Devices shipped in 13 reels QR e Commercial grade device with burn-in QB e Military grade device with environmental and burn-in processing shipped in tubes Temperature Range C e Commercial (b40 C to a 85 C) M e Military (b55 C to a 125 C) Physical Dimensions inches (millimeters) 28 Terminal Ceramic Leadless Chip Carrier (L) NS Package Number E28A 5 Physical Dimensions inches (millimeters) (Continued) 24 Lead Slim (0 300 Wide) Ceramic Dual-In-Line (SD) NS Package Number J24F 24 Lead Small Outline Integrated Circuit (S) NS Package Number M24B 6 Physical Dimensions inches (millimeters) (Continued) 24 Lead Slim (0 300 Wide) Plastic Dual-In-Line (SP) NS Package Number N24C 7 54ACT 74ACT823 9-Bit D Flip-Flop Physical Dimensions inches (millimeters) (Continued) Lit 114635 24 Lead Ceramic Flatpak (F) NS Package Number W24C LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user National Semiconductor Corporation 2900 Semiconductor Drive P O Box 58090 Santa Clara CA 95052-8090 Tel 1(800) 272-9959 TWX (910) 339-9240 National Semiconductor GmbH Livry-Gargan-Str 10 D-82256 F4urstenfeldbruck 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responsibility for use of any circuitry described no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications